The invention relates to semiconductors, and more particularly, to systems and processes for fabrication of semiconductor devices.
The proliferation of integrated circuit (IC) semiconductor devices into human society has been nothing short of phenomenal. The rapid technological advancements that occurred since the discovery of transistor devices in the 1940's has catapulted human innovation and spearheaded astonishing advancements. The immense power associated with computing power and signal processing continues to rapidly alter the fabric of our society.
As known in the art, the fabrication of integrated circuit devices is a multiple-step process. As general background, the fabrication of standard silicon-based chips starts with raw silicon dioxide, the most common component of sand or glass. The silicon dioxide is heated in the presence of hydrogen to produce pure silicon. The silicon is then melted and formed into ingots that are sliced into wafers. While silicon has traditionally been the most common semiconductor material, other materials such as gallium arsenide and germanium as well as others are used for certain applications depending upon the performance requirements.
These wafers will eventually be transformed in the integrated circuits after a number of processing steps are performed. In general, the process steps can be grouped into several basic areas: Front End Processing, Back End Processing, Test and Packaging.
The Front End Processing refers to the initial steps in the wafer fabrication process wherein the silicon wafers are created from very pure silicon ingots and actual semiconductor devices or transistors are fabricated on the wafers. A typical front end process includes preparing the wafer surface, patterning and implanting dopants to obtain the desired electrical properties, growing or depositing the gate dielectric, and growing or depositing insulating materials to isolate neighboring devices.
After the integrated circuit devices have been developed they are electrically interconnected and assembled to form the electrical circuits for the desired product. The Back End Processing involves depositing various layers of metal and insulating material in desired patterns of conducting and insulating layers to create the electrical pathways. In general, the conductive metal layers consist of aluminum or copper, although other metals are known in the art. The insulating layers are generally formed with silicon dioxide or a silicate glass however other materials are also known in the art. The conductive layers are interconnected by etching holes, called “vias” in the insulating material.
Advancements in the semiconductor industry have resulted in many distinct wafer fabrication processes, allowing designers to optimize a particular design by selecting the best process for the device. In general, fabrication processes simply consist of a series of steps to deposit special material layers on the wafers one at a time in precise amounts and patterns.
Once the Back End Processing has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine whether the integrated circuit device functions properly. Finally, the wafer is cut into individual die, which are then packaged in ceramic or plastic packages with pins or other connectors to the outside world.
The fabrication of circuits on the wafers thus requires that several different layers, each with different patterns, be deposited on the surface, and that doping of the active regions be done in very controlled amounts over tiny regions of precise areas. The various patterns used in depositing layers and doping regions on the substrate are defined by a process called photolithography. In general terms, photolithography refers to the process used in semiconductor device fabrication to transfer a pattern to the surface of a wafer or substrate. The transfer of this pattern allows for the definition of features to be etched in an underlying film or to provide a mask for ion implantation. In a complex integrated circuit a wafer may undergo photolithography multiple times.
In simple terms, the lithography process generally comprises applying at least one layer of photoresist material on the surface of a substrate. The resist layer is then selectively exposed to radiation with the exposed areas defined by the exposure device such as a mask. The photolithography or more succinctly, lithography, process generally commences with a layer of photoresist material that is spin-coated on the surface of the wafer. The resist is a light-sensitive material processed into specific patterns after being exposed to light energy in the shape of the desired pattern. The resist layer is then selectively exposed to radiation such as ultraviolet light, electrons, or x-rays, with the exposed areas defined by the exposure tool, mask or computer data.
After exposure, the photoresist layer is subjected to a development process. During development, the undesired areas in the photoresist are dissolved by the developer which dissolves undesired areas of the photoresist layer and exposes the corresponding areas of the underlying layer. Depending on the resist method, the development stage may dissolve either the exposed or unexposed areas. The areas with no resist material left on top of them are then subjected to additive or subtractive processes, allowing the selective deposition or removal of material on the substrate. In the case wherein the exposed areas become soluble in the developer, a positive image of the mask pattern is produced on the resist. Such a resist is therefore called a positive photoresist. Negative photoresist layers result in negative images of the mask pattern, wherein the unexposed areas are made soluble in the developer. Wafer fabrication may employ both positive and negative photoresists, although positive resists are generally used as they offer higher resolution capabilities.
The photoresist materials typically have three components, namely a matrix material or resin that provides body for the photoresist, an inhibitor or sensitizer which is the photoactive ingredient, and a solvent that keeps the resist in a liquid form until it is applied to the substrate.
Etching refers to the process of removing regions of the underlying material that are no longer protected by a photoresist and is typically described in terms of its level of isotropy. An isotropic etching process proceeds in all directions at the same rate, while an anisotropic etching process proceeds in only one direction. In general, etching processes fall between being completely isotropic and completely anisotropic. Wet etching, or etching with the use of chemicals tends to be isotropic while dry etching processes that employ reactive plasmas are generally anisotropic. The rate at which the etching occurs is known as the etch rate.
Thin films, as the name implies, is a layer with a high surface-to-volume ratio and are used in wafer fabrication. These films can be used to form a resistor, a conductor, an insulator, and even a semiconductor. The thin films can be deposited on a substrate by several means, such as thermal growing or by vapor deposition. A property of thins films is that they usually behave differently from bulk materials of the same chemical composition. For example, thin films are sensitive to surface properties, and relatively more sensitive to thermomechanical stresses. Furthermore, the thin films are influenced by the quality of adhesion to the underlying layer, the conformal coverage, residual or intrinsic stresses after deposition, and the presence of surface imperfections.
The adhesion of a thin film to the substrate or an underlying layer is one of the factors affecting the reliability of the thin film. A thin film that is initially adhered to the underlying layer but lifts off after the device is subjected to thermomechanical stresses may result in field failures. Reliable thin film adhesion depends upon many factors, including the cleanliness of the surface, and the roughness of the substrate/underlying layer among others. Regardless of the deposition process, thin films frequently end up with some intrinsic stresses that can lead to adhesion problems, corrosion, cracking, and deviations in electrical properties.
The metallization process refers to the formation of metal layers that electrically interconnect the various device structures fabricated on the silicon substrate. Aluminum and Gold are widely used materials for metallization, as they offer low resistivity and favorable adhesion compatibility with silicon dioxide. The metal layers may be deposited through Physical Vapor Deposition (PVD) by sputtering, which involves generating high-energy ions that bombard a target, and the ions sputter (eject) atoms from the target. The sputtered atoms reach the substrate and condense and form a thin film over the substrate.
The additive metallization technique known as “lift-off” was developed with the advent of electron beam lithography in the late 1960's. The lift-off techniques employ lift-off patterns and lift-off masks and the process is known in the art and described in “Integrated Circuit Fabrication Techniques”, by David J. Elliot, Copyright 1982 McGraw Hill, N.Y. The lift-off process employs a sacrificial material such as the photoresist that is deposited and patterned on the substrate. The material of interest is then deposited on top of the sacrificial material. The sacrificial material is then removed, leaving behind only the material deposited directly on the substrate. These processes are useful for patterning materials that cannot be etched without affecting underlying materials on the substrate. There are additional reasons for using lift-off as is known in the art.
One form of lift-off is realized through electron beam processing. The electron beam lift-off process provides the metallization after the exposure and development of the resist. Basically, the lift-off technique uses the fact that electron scattering in the resist and back scattering from the substrate creates a tear-shaped energy absorption profile in the resist, which results in an undercut profile after resist development. In this way metal that is evaporated over the entire surface exhibits discontinuities between the metal on the substrate and the metal over the resist. During resist removal in a suitable solvent, the metal over the resist is also removed and a clean reproduction of the image is obtained in metal. An additional advantage of the lift-off technique is that multi-level metal structures can be formed because any material or combination of materials that can be evaporated can be used.
One of the reasons for the success of the electron beam lift-off process in electron beam lithography is the fact that the energy absorption in the resist film during exposure is not linear but reaches a maximum in about two-thirds of the beam penetration range. Thus, with proper exposure and development, adequate undercut resist profiles are obtainable. In the optical exposure of photoresist, however, energy absorption is highest at the top of the resist film and lowest at the interface between the resist and the substrate due to the attenuation of the light in the resist. Moreover, standing waves created by the light reflected from the substrate are a further complication. These exposure conditions make it difficult to obtain undercut or even vertical resist profiles with normal UV exposure of azide type positive photoresist. Using ammonia based image reversal is one popular method to form lift-off profiles using positive azide based photoresists.
Early multilayer lift-off pattern systems were designed for use in processes where the processing temperature exceeded 100 degrees Celsius. However, processes which are employed in the manufacture of lead-base Josephson junction superconducting devices such as lead, lead alloys of gold, bismuth and indium have very thin oxide junctions which can be easily damaged when process temperatures exceeds 70 degrees Celsius.
The state of the art recognized the temperature problems involved in the manufacture of Josephson junction superconductive devices and provided a low temperature process solution. However, the saturated photoresist employed must be specially mixed and specially filtered, and the saturated photoresist material is sensitive to ambient temperatures. It is known that saturated photoresist materials have very low viscosity and must be applied in thin coatings. The processing employs multiple thin coatings of saturated photoresist. When the top layer of photoresist material is made too thin, and a substantial undercut lift-off pattern is being made, the top layer will collapse. Further, since the bottom layer of the photoresist lift-off pattern is substantially thicker than the top layer, longer development time is required to achieve a desired undercut and this permits the developing solution to attack and develop the top thin layer at the edges thus destroying the accuracy of the pattern. The saturated photoresist will combine with and bleed into the unsaturated layer that changes the concentration of both layers at the interface boundary.
Another technique known in the art in electron beam lithography to increase resist sensitivity while maintaining the undercut feature of the developed resist, comprises the coating of two or more resist layers having widely different solubilities. After electron beam exposure, a developer is chosen which develops the top layer much slower than the bottom layer. Alternatively, two mutually exclusive developers can be used for the successive development of the two layers. Both of these approaches result in resist profiles suitable for certain lift-off metallization.
Prior references such as U.S. Pat. No. 4,204,009 teaches a two-layer photoresist lift-off system employing two separate layers of positive photoresist material in which a lift-off pattern is provided at low processing temperatures. The first positive layer of photoresist material is thick and unsaturated. The second positive photoresist layer is comparatively thin and completely saturated. When the two layers are exposed as a laminate layer at the same time through a mask, the areas of both photoresist layers not covered by the mask are exposed to the collimated light source, and when the exposed areas are developed, they are removed. The use of a collimated light source for the denser and saturated upper layer of photoresist results in more isotropic or edge diffusion of the light into the edges of the bottom layer when both layers are exposed as a laminar structure. Furthermore, the edges of the bottom layer are more susceptible to light and are exposed to a greater degree. When the laminar structure is then developed, the bottom layer develops faster than the top layer, wherein the etched pattern extends under the resist, thereby limiting resolution of the pattern definition process.
The processing according to U.S. Pat. No. 5,889,788 employs the formation of resist patterns having two photoresist layers and an intermediate layer, which is another example using multiple layers to form vertical sidewalls. The first photoresist layer coats the substrate and is subjected to masking and exposure. And, the first photoresist is also subjected to develop. A transparent intermediate layer coats the developed first photoresist layer and a second photoresist layer is applied to the intermediate layer. The second photoresist layer is subjected to masking and exposure to form a second photoresist pattern. Etching is used so that the first and second photoresist patterns have a vertical pattern.
In the fabrication of semiconductor devices it is often desirable not only to form patterned conductive layers but also to fabricate conductive layers having some shape or form. For example, rounded chip pads (i.e. “solder balls”) enhance electrical contact with other metallization levels. Although there are many known methods for forming a patterned conductor layer on a substrate, the two common methods are subtractive etching and lift-off techniques. Of these two techniques, it has been found that lift-off is more desirable since the solvents used to remove the insulator in lift-off cause less damage to the underlying substrate than do the etch processes used in subtractive etching. Also, the conductor profile resulting from lift-off processing minimizes step coverage problems in subsequent conductor layers.
Thus, while lift-off techniques are a known method of forming patterned conductive layers, it would be of considerable advantage if these techniques could be utilized in order to form patterned conductive layers having varied shapes and complex forms. Furthermore, one of the problems known in the art is obtaining undercut and retrograde photoresist profiles in a controlled and reproducible manner. Another known problem with existing lift-off processing is the difficulty in lifting off metal patterns in first generation processing.
What is needed, therefore, are techniques for performing lithographic processes in a multi-layered system. Such techniques can be employed for enhanced liftoff processes and other applications that require large and controlled undercut. Such a system or process should operate at low processing temperatures and maintain very high accuracy of the mask dimensions.